Principal DFT Engineer

Role Overview

• Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.
• Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
• Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.
• Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.
• Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Requirements

• 10+ years in DFT, with at least 2 years in a leadership or principal role.
• Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Genus/Modus).
• Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).
• Proven track record with FinFET nodes (7nm, 5nm, or below).
• Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.