Floorplan development, power/ground distribution, and clock distribution.
Logic synthesis, cell placement, and interconnect routing.
Equivalence-checking, timing closure, and physical verification (LVS, DRC).
Strong collaboration with RTL designers to solve challenging problems.
Own and deliver digital subsystems of significant size/complexity.
Develop schedule and monitor progress.
Effective teamwork involving engineers working in geographically disparate locations.

B.Tech / M.Tech . in EE/ECE with 10+ years of experience in digital implementation.
Strong knowledge in Floor planning, place and route, CTS, STA, ECO methodology, Power analysis and Physical design verification.
Broad experience in synthesis and timing constraints.
Experience with 40nm digital implementation is essential.
Scripting skill and experience using languages such as Tcl , SKILL and Perl.
Knowledge of the state of the art implementation tools. Cadence tool experience preferred.
Experience working with Perforce/ Methodics for versioning.
Knowledge of CPF/UPF methodology is an added advantage.
Knowledge of Cadence virtuoso tool is an advantage.
Knowledge of foundry rules and ability to produce tape out ready GDS2 database is a plus.
Technical ownership and hands on expertise needed. Should be able to step in and take responsibility of implementation tasks when needed.
Strong inter-personal, teamwork and communication skills are required.

Staff Engineer, Physical Design

Key skills