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Principal RFIC Layout Designer at K2 Space Corporation | JobVerse
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Principal RFIC Layout Designer
K2 Space Corporation
Remote
Website
LinkedIn
Principal RFIC Layout Designer
United States
Full Time
3 weeks ago
$140,000 - $200,000 USD
No Visa Sponsorship
Apply Now
Key skills
Assembly
Leadership
About this role
Role Overview
Lead the end-to-end layout implementation of RF and mixed-signal blocks in advanced FinFET process nodes.
Own top-level layout integration for complex SoCs, including floorplanning, hierarchy definition, power distribution, and physical assembly.
Drive layout strategies to meet performance, area, power, reliability, and manufacturability targets.
Ensure robust implementation of matching and symmetry for sensitive RF/analog structures, and high-frequency routing and parasitic control.
Lead shielding, isolation, and substrate noise mitigation methodologies.
Ensure robust implementation of EM/IR, ESD, latch-up, and reliability considerations.
Define layout methodologies, guidelines, and best practices for RFIC and mixed-signal design in FinFET technologies.
Plan and manage layout schedules, milestones, and deliverables aligned with tapeout goals.
Collaborate closely with RF/analog designers, digital implementation teams, package/PCB engineers, and CAD to ensure seamless integration.
Manage and coordinate work with external layout vendors/contractors, including task definition, quality control, and schedule tracking.
Establish review processes (layout reviews, signoff checks, and quality metrics) to ensure first-pass silicon success.
Drive full-chip physical signoff, including DRC/LVS/ERC closure, EM/IR and reliability verification.
Own tapeout readiness and interface with foundry and EDA partners as needed.
Requirements
10+ years of RF/analog/mixed-signal layout experience, including leadership responsibilities.
Extensive hands-on experience with advanced FinFET process technologies (≤16nm preferred).
Proven track record of top-level SoC layout integration and successful silicon tapeouts.
Experience collaborating with distributed teams, including management of external layout vendors.
Deep understanding of RF and analog layout techniques and device physics, including high-frequency effects, parasitics, and isolation strategies.
Extensive hands-on experience with power planning and full-chip physical architecture.
Strong proficiency with industry-standard tools.
Tech Stack
Assembly
Benefits
Comprehensive benefits package including paid time off
Medical/dental/vision coverage
Life insurance
Paid parental leave
Equity in the company
Apply Now
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