3D Stacked Memory Architect

Role Overview

• Define next-generation 3D stacked memory architectures spanning bandwidth, capacity, power efficiency, and RAS
• Lead die-to-system co-optimization across memory die, PHY, TSVs, bonding, packaging, and system integration
• Architect stack-aware RAS, telemetry, and reliability mechanisms for high-density memory systems
• Drive long-range technology strategy for stacked memory and advanced packaging
• Engage deeply with customers, platform partners, and standards bodies to influence system and ecosystem direction

Requirements

• Bachelor’s degree or equivalent practical experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Extensive industry experience in stacked memory, 3D integration, advanced packaging, or high-performance semiconductor architecture
• Deep hands-on expertise in high-speed I/O, TSV-based stacking, power delivery, thermals, and signal integrity
• Proven ability to translate system-level requirements into memory and package architecture
• Demonstrated technical leadership across teams and complex architectural decisions
• Master’s degree or PhD in Electrical Engineering or a related technical field (preferred)
• Recognized expertise in stacked memory or advanced packaging, internally or externally (preferred)
• Experience influencing tier-1 customers, platform architects, or industry standards (preferred)
• Track record of architectural innovations shipped in production silicon or platforms (preferred)
• Experience mentoring senior engineers or architects (preferred)

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays