Key skills
AIML
About this role
Role Overview
- Develop innovative memory subsystem frameworks for HBM solutions supporting AI/ML workloads
- Define Memory and RAS architecture requirements and drive architectural planning for next generation memory subsystems
- Collaborate with internal and external partners to develop novel architectures and detailed IP requirements
- Lead engagement with IP vendors, including evaluation and selection of interface and functional IP
- Analyze benchmarks, workloads, and simulations to identify opportunities for performance, efficiency, and architectural innovation
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
- Minimum of 12 years of experience in memory subsystem architecture and design
- Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM)
- Experience with PHY design and understanding of signal integrity issues
- Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, etc.
Benefits
- Choice of medical, dental and vision plans
- Income protection programs
- Paid family leave
- Robust paid time-off program
- Paid holidays