play a pivotal role in extraction and static timing analysis (STA) flow development
develop methodologies, guidelines, and checklists to streamline STA work
resolve design and flow issues
drive execution to ensure progress and accuracy

Bachelor’s degree in Electrical or Computer engineering and 5+ years of ASIC Design experience, or Master's degree in Electrical or Computer Engineering and 3+ years of experience, or PhD + 0 years of experience
Experience with Verilog/SystemVerilog programming
Prior STA experience is a plus
Strong written and verbal communication skills

medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
flexible vacation time off program, with no defined limit
80 hours of sick time off provided on hire date and each January 1st thereafter
additional paid time away may be requested for critical or emergency issues for family members
optional 10 paid days per full calendar year to volunteer
employees are also eligible to earn annual bonuses

ASIC STA Engineer

Key skills