Lead package design tasks, planning and driving schedules from concept through implementation
Optimize package pinouts, stack-ups, power distribution, and high-speed routing, balancing performance and manufacturability
Collaborate with silicon floor planning, signal integrity (SI), and power integrity (PI) teams to ensure design quality and efficiency
Work closely with layout editors to deliver high-quality package designs aligned with interface requirements
Enhance design methodologies and partner with vendors to improve product quality and efficiency
Drive innovation in package solutions for Cisco’s next-generation ASICs

12+ years of experience
Bachelor’s or Master’s degree in Electrical Engineering or related field
Strong understanding of high-speed signal design, power distribution networks (PDN), and PCB design
Experience with industry-standard EDA tools for layout and design
Scripting experience (Python, Perl, TCL, shell programming) is highly valuable
Experience in ASIC package design including pinout optimization and high-speed routing
Knowledge of silicon floor planning, SI, and PI considerations
Proven ability to lead design improvements and coordinate with stakeholders
Firsthand experience with testing and measurement equipment (oscilloscopes, TDR/VNA analyzers)
Excellent verbal and written communication skills in English

Lead Hardware Engineer, IC Package Design

Key skills