Key skills
Computer architectureDigital logic designSystemVerilogPower Performance Area (PPA)Digital logic synthesis toolsStatic Timing Analysis (STA)AI workload accelerationGit version controlPython scriptingLinux Shell scriptingPythonShellAIGenerative AIGitVersion Control
About this role
SambaNova Systems is a leader in generative AI technology, providing a comprehensive platform optimized for enterprise and government organizations. The Hardware Design Engineer role focuses on designing components for ASICs in AI workload acceleration systems, collaborating with various engineering teams to enhance hardware features.
Responsibilities:
- Define and document microarchitecture specifications for complex digital design elements for compute, memory, or networking subsystems
- Code, integrate, and debug SystemVerilog RTL designs through the chip implementation and production lifecycle
- Meet targets for Power, Performance and Area (PPA) using advanced digital design techniques for high-speed design
- Work alongside design verification and physical design team owners to converge
- Work with architects and software teams to prototype new features which improve application-level performance
- Mentor junior design engineers on high-speed digital design techniques
- Drive improvements into the design flow using AI and automation, including new EDA tool methodologies
Requirements:
- Minimum required education: Master's or PhD degree in Computer Engineering or Electrical Engineering
- Computer architecture and digital logic design
- Knowledge of AI workload acceleration techniques and industry standard interconnects and protocols (e.g. AXI, PCIe, Ethernet, HBM/DDR)
- Mastery of SystemVerilog design techniques for high speed, high performance ASICs
- Demonstrated skill in converging functionality while making design decisions trading off Power, Performance, and Area (PPA)
- Experience in digital logic synthesis tools and Static Timing Analysis (STA)
- Proficiency in using industry standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC)
- Proficiency in using tools and simulators for hardware performance analysis and tuning
- Experience implementing SystemVerilog Assertions (SVA) for checking design intent
- Familiarity with Git version control tool for managing release cycles
- Scripting skills in Python and Linux Shell