ASIC Engineering Technical Leader, STA

Cisco is a leading technology company revolutionizing how data and infrastructure connect and protect organizations. They are seeking an ASIC Engineering Technical Leader to define, design, and verify timing constraints for ASICs, contributing to a multi-disciplined engineering team to meet performance goals for their products.

Responsibilities:

• Closing timing at block, sub-chip, and full-chip levels, as well as performing quality checks such as setup, holds, transition, and noise, while running ECO tasks
• Extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with assisting the Physical Design team with standard methodologies
• Additionally, you’ll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy

Requirements:

• Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master's degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of ASIC Design experience
• Experience in generating timing constraints and performing quality checks such as setup, hold, transition, and noise
• Proven experience with timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recover, as well as familiarity with various on-chip variations
• Proficient in synthesis constraints and using industry standard synthesis tools
• Prior experience leading and/or mentoring junior STA engineers
• Experience resolving setup and hold timing violations with RTL modification
• Good written and verbal communication skills