Physical Design Engineer New Grad

JDWK, Inc. is a startup seeking a curious and driven new graduate to join their team as an Associate Physical Design Engineer. The role involves training and mentorship across the RTL-to-GDS flow, focusing on chip implementation and software development for design automation.

Responsibilities:

• Run RTL2GDS tools through various designs and experiments while improving automation
• Learn to translate RTL (Verilog/SystemVerilog) into a gate-level netlist using industry-standard tools
• Learn how to partition a chip's physical space — placing memories, hard macros, and IO
• Learn to place standard cells and route metal interconnect across a design
• Understand how clock signals are distributed across a chip and learn to build balanced, low-skew clock trees
• Learn static timing analysis (STA) — how to read and interpret timing reports
• Learn to analyze dynamic and static power consumption and understand how power grid integrity is verified and fixed
• Learn to run and interpret DRC (Design Rule Check), LVS (Layout vs. Schematic), and antenna checks
• Learn what it means to sign off a chip for manufacturing, including final checks, GDSII delivery, and documentation
• Read and understand Verilog and SystemVerilog RTL written by front-end designers
• Identify constructs in RTL that negatively impact synthesis quality, timing, or physical implementation
• Communicate clearly and constructively with front-end engineers about RTL changes that improve PPA
• Develop an understanding of microarchitecture well enough to anticipate implementation challenges before they arise
• Write production-quality TCL scripts to automate tool interactions, manage constraints, parse results, and control flow execution
• Develop Python tools for data processing, report generation, flow automation, and regression testing
• Read and contribute to software codebases shared across the CAD and PD teams
• Use Git for version control and contribute to shared repositories following team standards
• Explore and apply LLM-assisted workflows to accelerate code writing, debugging, and testing tasks
• Learn to submit, monitor, and debug jobs on compute clusters using schedulers such as LSF or Slurm
• Become comfortable working in Linux environments, writing shell scripts, and managing EDA run directories and configurations
• Develop the ability to diagnose and resolve common environment, storage, and licensing issues that arise during design runs

Requirements:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field (completed or completing)
• Coursework in digital logic design, VLSI design, computer architecture, or electronic circuits is highly relevant
• Solid understanding of digital logic — combinational and sequential circuits, finite state machines, timing concepts
• Some programming experience in Python, TCL, or any scripting/systems language — we will build from wherever you are
• Familiarity with Verilog or SystemVerilog, even at a coursework level, is a meaningful advantage
• Comfort working in a Linux/Unix command-line environment
• Genuine intellectual curiosity — you want to understand not just how to run a step, but why it works the way it does
• Strong written and verbal communication skills; able to ask good questions and articulate what you do and don't understand
• Comfortable with ambiguity and self-directed learning in a startup environment where not everything is documented
• Detail-oriented and methodical — chip implementation rewards precision, and mistakes caught early are far cheaper than mistakes caught late
• Collaborative and low-ego — willing to learn from senior engineers and equally willing to share what you discover
• Internship, research, or project experience involving VLSI implementation, FPGA design, or EDA tooling
• Exposure to open-source EDA tools such as OpenROAD, Yosys, or KLayout
• Any experience with C++, Rust, or web technologies (HTML/CSS/JS)
• Contributions to open-source projects or a portfolio of personal engineering work
• Familiarity with AI/LLM tools applied to code generation or engineering automation