Physical Design Engineer

JDWK, Inc. is a startup seeking an exceptional Physical Design Engineer who combines semiconductor implementation expertise with strong software engineering skills. The role involves owning the full RTL-to-GDS flow and contributing to design automation software while collaborating with CAD engineers and front-end designers in a dynamic environment.

Responsibilities:

• Own and execute the full RTL-to-GDS flow including synthesis, floorplanning, place and route, clock tree synthesis, timing closure, power analysis, physical verification (DRC/LVS), and sign-off
• Drive timing closure across complex hierarchical designs, resolving setup, hold, and noise violations with methodical precision
• Develop and optimize floorplans with a strong understanding of power, performance, and area (PPA) tradeoffs
• Perform power integrity analysis and work with power grid construction to meet IR drop and EM targets
• Execute and interpret results from physical verification including DRC, LVS, ERC, and antenna checks
• Support tapeout activities including final sign-off, GDSII delivery, and post-tapeout documentation
• Read, analyze, and modify RTL (Verilog/SystemVerilog) to resolve implementation issues or improve PPA
• Provide clear, constructive, and technically rigorous feedback to front-end and RTL designers on coding style, synthesis constraints, and design-for-implementation best practices
• Participate in design reviews, identifying upstream issues that impact physical implementation early in the cycle
• Develop and enforce RTL coding guidelines that improve synthesis quality and reduce implementation iterations
• Actively contribute to internal EDA automation software — writing, debugging, and testing production-quality code as a core part of the role
• Develop and maintain TCL and Python scripts for flow automation, result parsing, constraint management, and reporting
• Write and execute test cases for design automation tools; participate in code reviews and help define QA standards
• Identify gaps and inefficiencies in existing flows and propose or implement tooling improvements
• Collaborate with CAD engineers to integrate new features into the RTL-to-GDS automation platform
• Manage job submission and compute resource allocation using grid/cluster managers such as LSF or Slurm
• Maintain and improve flow infrastructure including directory structures, configuration management, and run environments
• Assist with onboarding of new EDA tool versions, license management, and environment setup
• Troubleshoot compute, storage, and environment issues that arise during design runs

Requirements:

• 5+ years of hands-on experience with full RTL-to-GDS flows at advanced nodes (28nm or below strongly preferred)
• Proficiency with industry-standard implementation tools from Cadence (Genus, Innovus, Tempus, Voltus) and/or Synopsys (Design Compiler, ICC2, PrimeTime, StarRC)
• Deep understanding of static timing analysis, constraint development (SDC), and multi-corner multi-mode (MCMM) closure
• Strong grasp of physical verification flows and sign-off criteria
• Experience with floorplanning methodologies for hierarchical and flat designs
• Ability to read, understand, and modify Verilog and/or SystemVerilog RTL with confidence
• Demonstrated experience giving actionable implementation feedback to RTL and front-end design teams
• Familiarity with synthesis constraints, timing exceptions, and their implications on physical implementation
• Expert-level TCL scripting — ability to write, debug, and refactor complex tool automation scripts
• Strong Python skills, including experience with data parsing, flow automation, and report generation
• Comfort reading and contributing to software codebases; experience writing tests and participating in code reviews
• Familiarity with version control (Git) and CI/CD practices in an engineering environment
• Comfort with Linux system administration, shell scripting, and managing EDA run environments
• Experience with compute cluster job scheduling (LSF, Slurm, or equivalent)
• Ability to debug environment, compute, and storage issues independently
• C++ proficiency — ability to read, modify, and contribute to C++ codebases within EDA tools or automation frameworks
• Experience with Rust for systems-level tooling or performance-critical automation components
• HTML/web skills for building internal dashboards, result viewers, or reporting interfaces
• Experience with open-source EDA tools such as OpenROAD, Yosys, or KLayout
• Knowledge of design automation frameworks such as FDL, Flowtool, or Lynx
• Experience with LLM-assisted code generation or AI-driven design automation workflows
• Exposure to analog/mixed-signal, memory, or custom cell implementation flows
• Prior experience at an EDA vendor, fabless semiconductor company, or hardware startup