Lead Solutions Engineer – Runset Enablement (Physical Verification)

Cadence is a technology company focused on developing leaders and innovators. They are seeking a Lead Solutions Engineer specializing in runset enablement to support advanced semiconductor technologies, responsible for the development and validation of physical verification solutions.

Responsibilities:

• Lead development and validation of Pegasus DRC and LVS runsets for advanced nodes
• Architect automation frameworks for regression execution, issue detection, and validation reporting
• Collaborate with R&D to resolve CCRs, influence product roadmap, and implement performance improvements
• Provide technical enablement and support for customers on tool usage and advanced methodologies
• Mentor junior engineers and establish best practices for runset development and QA
• Work closely with internal teams to ensure timely delivery of verification solutions

Requirements:

• MS degree with 5+ years of experience or PhD with 3+ years in Electrical Engineering, Computer Science, or related field
• Strong understanding of semiconductor design and physical verification flows
• Proven expertise in developing and validating DRC and LVS runsets for Pegasus or similar tools (Calibre, ICV, Assura)
• Deep knowledge of advanced process technologies and methodologies (Ground Rules, SmartFill, ESD)
• Proficiency in scripting languages (TCL, Python, Perl) and Linux/Unix environments
• Familiarity with chip fabrication processes and multi-die integration challenges
• Experience in automation frameworks for regression and validation
• Strong leadership and mentoring capabilities
• Excellent written, verbal, and presentation skills
• Ability to influence cross-functional teams and drive strategic initiatives
• Innovative mindset to explore unconventional solutions and optimize workflows
• Operate with integrity and foster collaboration across global teams
• Good-to-have: Experience with PERC and Fill runsets