Principal Mixed-Signal IC Design Engineer

K2 Space Corporation is building the largest and highest-power satellites ever flown, aiming to unlock unprecedented performance levels in space technology. They are seeking a Principal Mixed-Signal IC Design Engineer to lead the design and development of advanced mixed-signal SoCs for satellite communications, focusing on high-speed data converters and PLL designs.

Responsibilities:

• Lead the design and development of high-performance, high-speed ADC and DAC architectures
• Lead the architecture definition and implementation of low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems
• Own the planning and execution of simulations for critical mixed-signal sub-systems at the transceiver level to ensure system performance and compliance
• Own the package design strategy, modeling, and cross-functional integration
• Lead cross-functional efforts to integrate circuits advanced FinFET-based SoCs, ensuring layout, parasitic, and floor planning alignment
• Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation
• Perform design optimization for power, area, and performance in advanced FinFET nodes
• Develop and maintain design documentation and support post-silicon bring-up and characterization
• Support your product through production and spaceflight
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team

Requirements:

• M.S. or Ph.D. in Electrical Engineering with a strong focus in analog/mixed-signal IC design
• 10+ years of relevant industry experience in mixed-signal circuit design
• Proven hands-on experience in high-speed ADC/DAC designs with deep understanding of architectures, performance metrics, and design trade-offs
• Deep understanding of PLL design principles, including charge pump, VCO, loop filter, multi-modulus divider, sigma delta modulator, and jitter analysis
• Experience with FinFET CMOS process characteristics and layout parasitic considerations
• Proficient in EDA tools such as Cadence Virtuoso, Spectre, behavioral modeling (Verilog-A, Verilog-AMS, MATLAB), and similar tools
• Strong debugging, problem-solving, and communication skills
• Deep knowledge of data converter and PLL architectures and their trade-offs, systems specifications, and ability to translate system requirements into circuit requirements
• Tape-out experience in advanced FinFET nodes
• Hands-on experience implementing digital calibration techniques and DSP-assisted mixed-signal systems
• Solid understanding of and experience with building block circuits such as bandgaps, bias generators, TIAs, op-amps, filters, and LDOs
• Exposure to EM/Reliability/ESD design best practices
• Experience working in cross-functional, geographically distributed teams